Heeft iemand enig idee wat deze code doet?? Hoe het werkt??
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity pwm is
port ( ena_nv : in std_logic;
new_value : in std_logic_vector(7 downto 0);
clk : in std_logic;
pwm_out : out std_logic
);
end pwm;
architecture pwm_arch of pwm is
signal load : std_logic := '1';
signal updwn : std_logic := '0';
signal mark_value, fcount : std_logic_vector (7 downto 0) := "00000000";
begin
mark_register : process (clk)
begin
if (clk'event and clk = '1') then
if ena_nv = '1' then
mark_value <= new_value;
end if;
end if;
end process mark_register;
frame_counter : process (clk)
begin
if (clk'event and clk = '1') then
if load = '1' then
fcount <= mark_value;
else
if updwn = '1' then
fcount <= fcount + 1;
else
fcount <= fcount - 1;
end if;
end if;
end if;
end process frame_counter;
load <= '1' when (fcount = "00000000" or fcount = "11111111") else '0';
pwm : process (clk)
begin
if (clk'event and clk = '1') then
if load = '1' then
updwn <= not updwn;
end if;
end if;
end process pwm;
pwm_out <= updwn;
end pwm_arch;
